COPPER LAYER SHEET RESISTANCE EVOLUTION AS A FUNCTION OF POST-SEED PROCESS SELF-ANNEALING TIME
Copper layer metallization is one of the important processes in integrated circuit manufacturing. One of the issues faced in this process is the proneness of Cu interface diffusion as well as surface oxidation which degrade some of the Cu thin film properties. Due to this concern, most integrated circuit manufacturing facility imposed 12 hours maximum delay time between the Cu seed deposition and Cu electroplating step. However, there is lack of study and data to justify support this time restriction. This study investigated the effect of self-annealing time between Cu seeding process and Cu electroplating process to the sheet resistance, reflectance, and stress of the deposited film. The data indicated that the there is no significant deterioration or fluctuation in sheet resistance, reflectance, and stress beyond 12 hours delay time. This suggested that the imposed 12 hours maximum delay time between Cu seed and Cu electroplating process can be further extended, which will give greater flexibility for the manufacturing scheduling.
F. Wei, L. Li and L. Liu, “Facile synthesis of copper nanostructures through simple replacement reaction,” in 10th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, Xi’an, China, 2015, pp. 160-163.
J.W. Lim, Y. Ishikawa, K. Miyake, M. Yamashita and M. Isshiki, “Influence of substrate bias voltage on the properties of cu thin films by sputter type ion beam deposition”, The Japan Institute of Metals. Materials Transactions, vol. 43, no. 6, pp. 1403-1408, 2002.
R. W. Vook, “Electrical control of surface electromigration damage”, Thin Solid Films, vol. 305, no. 1-2, pp. 286-291, 1997.
L. Pryor, R. Schlobohm and B. Brownell. (2008). A Comparison of Aluminum vs. Copper as Used in Electrical Equipment [Online].
D. Edelstein, C. Uzoh, C. Cabral, P. DeHaven, P. Buchwalter, A. Simon, E. Cooney, S. Malhotra, D. Klaus, H. Rathore, B. Agarwala and D. Nguyen, “A high-performance liner for copper damascene interconnects,” in IEEE 2001 International Interconnect Technology Conference, Burlingame, California, 2001, pp. 9-11.
K. Pantleon and M. A. J. Somers, “In situ investigation of the microstructure evolution in nanocrystalline copper electrodeposits at room temperature”, Journal of Applied Physics, vol. 100, no. 11, pp. 114319-114326, 2006.
W. Wu, D. Ernur, S.H. Brongersma, M. Van Hove, and K. Maex, “Grain growth in copper interconnect lines”, Microelectronic Engineering, vol. 76, no. 1–4, pp. 190–194, 2004.
R. Huang, W. Robl, H. Ceric, T. Detzel and G. Dehm , “Stress, sheet resistance, and microstructure evolution of electroplated cu films during self-annealing”, IEEE Transaction on Device and Materials Reliability, vol. 10, no. 1, pp. 47-54, 2010.
S. P. Hau-Riege and C. V. Thompson, “In situ transmission electron microscope studies of the kinetics of abnormal grain growth in electroplated copper films”, Applied Physics Letters, vol. 76, no. 3, pp. 309–311, 2000.
J. M. E. Harper, C. Cabral Jr., P. C. Andricacos, L. Gignac, I. C. Noyan, K. P. Rodbell and C. K. Hu, “Mechanisms for microstructure evolution in electroplated copper thin films near room temperature”, Journal of Applied Physics, vol. 86, no. 5, pp. 2516-2525, 1999.
B.A. Tik Sun, “Classical size effect in copper thin film: Impact of surface and grain boundary scattering on resistivity,” Ph.D. dissertation, Department of Mechanical, Materials, and Aerospace Engineering, University of Central Florida, Orlando, Florida, 2005.
G. Brunoldi, S. Guerrieri, S.G. Alberici, E. Ravizza, G. Tallarida, C. Wiemer and T. Marangon, “Self-annealing and aging effect characterization on copper seed thin films”, Microelectronic Engineering, vol. 82, no. 3-4, pp. 289–295, 2005.
S. Lagrange, H. Brongersma, M. Judelewicz, A. Saerens, I. Vervoort, E. Richard, R. Palmans and K. Maex, “Self-annealing characterization of electroplated copper films”, Microelectronic Engineering, vol. 50, no. 1, pp. 449– 457, 2000.
W. H. Teh, L. T. Koh, S. M. Chen, J. Xie, C. Y. Li and P. D. Foo, “Study of microstructure and resistivity evolution for electroplated copper films at near-room temperature”, Microelectronics Journal, vol. 32, no. 7, pp. 579–585, 2001.