OPTIMIZATION OF COPPER VIA FILLING PROCESS FOR FLEXIBLE PRINTED CIRCUIT USING RESPONSE SURFACE METHODOLOGY
Abstract
Copper filling is a method for 3D stacked packaging and has been widely used in the semiconductor industry. However, as the downsizing of devices becomes an unavoidable trend, the tolerance of flexible printed circuit (FPC) fabrication has to decrease, resulting in high failure rates. To solve this problem, optimal process variables for copper filling must be studied to avoid the risk of failure. In this study, the effects of copper via filling parameters (current density (Id), fluid flow rate (Q) and filling time (tf)) on the filling behavior of a micro via (surface thickness, dimple depth and via filling ratio) were investigated. The via on the FPC board was drilled using a laser drill with a dimension of 100 µm. Then, the FPC was immersed in an electrolyte for the copper via filling process. Experimental results showed that current density was significant to surface thickness, whereas fluid flow rate was significant to the dimple depth and via filling ratio. The optimum parameters to achieve thin surface thickness, low dimple depth and high via filling ratio were found to be at 1.5 A/dm2 of current density, 35 m3/h of fluid flow rate and 60 min of filling time.
Downloads
References
[2] M. Schlesinger and M. Paunovic, Modern Electroplating, 5th Edition. New Jersey: John Wiley and Sons, 2010.
[3] H. Huebner, R.S. Mertens and D. Ruess, “Copper filling of blind micro vias and through holes using reverse pulse plating,” PCB Magazine 007, vol. 4, no. 5, pp. 24–34, 2014.
[4] M.Y. Yen, M.H. Chiang, H.H. Tai, H.C. Chen, K.W. Yee, C. Li, M. Lefebvre and M. Bayes, “Next generation electroplating technology for high planarity, minimum surface deposition microvia filling,” in International Microsystems, Packaging, Assembly and Circuits Technology Conference, Taiwan, 2012, pp. 259–262.
[5] F. Wang, Z. Zhao, N. Nie, F. Wang and W. Zhu, “Effect of via depth on the TSV filling process for different current densities,” Journal of Micromechanics and Microengineering, vol. 28, no. 4, pp. 1–11, 2018.
[6] A.B. Hadzley, W.M. Azahar, A.A. Anis, R. Izamshah, M. Amran, S. Kasim and S. Noorazizi, “Development of surface roughness prediction model using response surface methodology for end milling of HTCS-150,” Journal of Advanced Manufacturing Technology, vol. 12, no. 1, pp. 467–476, 2018.
[7] F. Wang, W. Liu and Y. Wang, “Effects of additives with different acids on the through-silicon vias copper filling,” Microelectronic Engineering, vol. 200, pp. 51–55, 2018.
[8] Y. Zhu, W. Luo, Z. Chen, M. Li and L. Gao, “Influence of electroplating current density on through silicon via filling,” in International Conference on Electronic Packaging Technology, China, 2015, pp. 153–157.
[9] W. Engelmaier and T. Kessler, “Investigation of agitation effects on electroplated copper in multilayer board plated-through holes in a forced-flow plating cell,” Journal of The Electrochemical Society, vol. 125, no. 1, pp. 36–43, 1978.
[10] H. Pan, Y. Zhang, M. Li and L. Gao, “Effect of pretreatment on copper filling of high aspect patio through-silicon via (TSV),” in International Conference on Electronic Packaging Technology, China, 2018, pp. 672–675.
[11] F. Wang, Z. Zhao, F. Wang, Y. Wang and N. Nie, “A novel model for through-silicon via (TSV) filling process simulation considering three additives and current density effect,” Journal of Micromechanics and Microengineering, vol. 27, no. 12, pp. 1–12, 2017.
[12] M. Nikolova, C. Rodriguez, K. Feng, C. Gugliotti, W. Bowerman, J. Watkowski and B. Wei, “Via fill and through hole plating process with enhanced TH microdistribution,” PCB Magazine 007, vol. 8, no. 11, pp. 78–90, 2018.
[13] W.P. Dow, M.Y. Yen, S.Z. Liao, Y.D. Chiu and H.C. Huang, “Filling mechanism in microvia metallization by copper electroplating,” Electrochimica Acta, vol. 53, no. 28, pp. 8228–8237, 2008.
[14] M. Nagai, Y. Tamari, N. Saito, F. Kuriyama, A. Fukunaga, A. Owatari, S. Masashi and C. Moore, “Electroplating copper filling for 3D packaging,” in Electronic Components and Technology Conference, USA, 2009, pp. 648–653.
[15] J. Wang, M. Wu and C. Cui, “Factors governing filling of blind via and through hole in electroplating,” Circuit World, vol. 40, no. 3, pp. 92–102, 2014.
