Remote Global Alignment Error for Cycle Time Improvement of Pad Inductor Layer
Lithography is the key process which transfers the pattern from mask to wafer and pad inductor layer is the last layer in photo masking. The cycle time for pad inductor layer increase in Silterra Malaysia by 32% of Global Alignment error per month. This induce success rate goes down as low as 50% for pad inductor layer. Long engineering time is taken during troubleshooting of the lot for expose and developing step by manually due to tool time constrain. Most of the lots undergo rework processes which results the cost per wafer to increase. The aim of this research is to reduce the cycle time for pad inductor layers by introducing the “Remote Global Alignment Error” (RGAE) method with alternative flow. This would avoid the pad inductor layers to be sent for rework if it encountered any global alignment error. The experimental result shows RGAE method able to reduce cycle time for pad inductor layer by 97%. This is due to when global alignment error occurs the lot will automatically track in RGAE method by selecting the rejected wafers for expose and developing process. This has eventually saved more time for split wafers which usually send for rework.
H.J. Levinson, Principles of Lithography. Washington USA: SPIE Press, 2005.
N.R. Yazdani, E.M. Apelgren, R.D. Edwards, M.A. Simmons and S.E. Brown, “Extending the life of ttl-alignment steppers to 65-nm technology”, in the International Symposium on Semiconductor Manufacturing, Santa Clara, CA, 2007, pp. 1-4.
S.Y. Tien, “Cycle time analysis for photolithography tools in semiconductor manufacturing industry with simulation model,” M.S. thesis, School of Mechanical Engineering, University Sains Malaysia, Penang, Malaysia, 2008.
J.T. Spierings, “Cycle time analysis of photolithography systems in a semiconductor manufacturing plant,” M.S. thesis, Department of Mechanical Engineering, Eindhoven University, Eindhoven, Netherlands, 2013.
J.J.R. Van Der Eerden, H.G. Niesing and J.E. Rooda, Litho area productivity improvement., Netherlands: ASML, Eindhoven, 2016.
M. Lentz, Industry economic model & enterprise value of cycle time. Hsinchu: SEMATECH, 2011.
A. Cherala, “Nanoscale magnification and shape control system for precision overlay in jet and flash imprint lithography”, IEEE/ASME Transactions on Mechatronics, vol. 20, no. 1, pp. 122-132, 2015.
M. Baum, L. Hofmann, M. Wiemer, S. Schulz and T. Gessner, “Development and characterisation of 3D integration technologies for mems based on copper filled tsv's and copper-to-copper metal thermo compression bonding”, in the International Semiconductor Conference Dresden - Grenoble (ISCDG), Dresden, 2013, pp. 1-4.
W. Flack, “Lithography technique to reduce the alignment errors from die placement in fan-out wafer level packaging applications,” in the IEEE 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, FL, 2011, pp. 65-70.
X. Dong, “Method of improving enhance alignment quality in double patterning with spacer process for 14–16nm FinFET," in the China Semiconductor Technology International Conference, Shanghai, 2015, pp. 1-3.
D.S. Temple, E.P. Vick, M.R. Lueck and D. Malta, “Scaling of 3D interconnect technology incorporating metal-metal bonds to pitches of 10 microns and below for infrared focal plane array applications,” Japanese Journal of Applied Physics, vo. 54, pp. 030202-1-030202-7, 2015.
P. Wafer, W. Packaging, U. Eutectic and M. Bonding, “Precision wafer to wafer packaging using eutectic metal bonding,” SUSS Report, Germany, 2008.
S.H. Lee, K.N. Chen and J.J.Q. Lu, “Wafer-to-wafer alignment for three-dimensional integration: a review”, Journal of Microelectromechanical Systems, vol. 20, no. 4, pp. 885-898, 2011.
L.Y. Yen and K.H. Chang, “Cycle time reduction for photolithography area with multi-workstation,” in the Proceedings of the 2012 IEEE 16th International Conference on Computer Supported Cooperative Work in Design (CSCWD), Wuhan, 2012, pp. 742-746.
T. Chen, “A systematic cycle time reduction procedure for enhancing the competitiveness and sustainability of a semiconductor manufacturer”, Sustainability, vol. 5, no. 11, pp. 4637–4652, 2013.
Authors who publish with this journal agree to the following terms:
- Authors transfer copyright to the publisher as part of a journal publishing agreement with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
- Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
- Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) after the manuscript is accepted, as it can lead to productive exchanges, as well as earlier and greater citation of published work (See The Effect of Open Access).