# FIXED-POLE ACTIVE PI FILTER DESIGN FOR HIGH FREQUENCY NONLINEAR PLL MODELS

### Abstract

A Phase-locked loop (PLL) is a basic control system that attempts to produce an output waveform that can match with the input reference signal in the shortest time possible. A filter is one of the main components in the PLL blocks, and it plays a very important role to determine the range of input frequency that can ensure the system stays in a locked condition. This paper focuses on designing a fixed-pole active PI filter which is suitable for high-frequency PLL-based circuits such as those used in clock generators. As PLL is bound to fall out of lock due to the nonlinear effects from its phase detector, a new approach is introduced in this work which is to combine the linear and nonlinear control method to ensure stability. Having had the phase margin specified a priori, it is shown by simulation that the allowable range of input frequency such that the system remains locked can be expanded.

### Downloads

### References

A. Gameiro, “An Extended Phase-Locked Loop for Clock Synchronization Applications,” in Global Telecommunications Conference, San Francisco, USA, 1994, pp. 956–961.

S. Stevanovic and B. Pervan, “A GPS phase-locked loop performance metric based on the phase discriminator output,” Sensors, vol. 18, no. 1, pp. 1-23, 2018.

G. Bhargav, G. Prasad, S.D. Canchi, and B. Chanikya, “Design and analysis of phase locked loop in 90nm CMOS,” in Thirteenth International Conference on Wireless and Optical Communications Networks (WOCN), Hyderabad, Telangana State, India, 2016, pp. 1–7.

A. Grebene and H. Camenzind, “Phase locking as a new approach for tuned integrated circuits,” in IEEE International Solid-State Circuits Conference. Digest of Technical Papers, Philadelphia, USA, 1969, pp. 100–101.

A.B. Gregene. and H.R. Camenzind, “Frequency-selective integrated circuits using phase-lock techniques,” IEEE Journal of Solid-State Circuits, vol. 4, no. 4, pp. 216–225, 1969.

B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design. New Jersey: John Wiley & Sons, 1996.

B.K . Mishra, S. Save and S. Patil, “Design and Analysis of Second and Third Order PLL at 450MHz,” International Journal of VLSI Design and Communication Syststem, vol. 2, no. 1, pp. 97–114, 2011.

E. Ozeren, S. Zihir, F. Tasdemir, I. Tekin and Y. Gurbuz, “A Fully Integrated Multiband Frequency Synthesizer for WLAN and WiMAX applications,” in the 5th European Microwave Integrated Circuits Conference, Paris, France, 2010, pp. 369–372.

V. Valenta, M. Villegas and G. Baudoin, “Analysis of a PLL Based Frequency Synthesizer using Switched Loop Bandwidth for Mobile WiMAX,” in 18th International Conference Radioelektronika, Prague, Czech Republic, 2008, pp. 1–4.

I.A. Young, J.K. Greason and K.L. Wong, “A PLL clock generator with 5 to 110 MHz of lock range for microprocessors,” IEEE Journal of Solid-State Circuits, vol. 27, no. 11, pp. 1599-1607, 1992.

F.M. Gardner, Phaselock Techniques. New York: John Wiley & Sons, 2005.

R.E. Best, Phase-Locked Loops: Design, Simulation, and Application. New York: McGraw-Hill, 2007.

K. Kishine, K. Fujimoto, S. Kusanagi and H. Ichino, “PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits,” IEEE Journal Solid-State Circuits, vol. 39, no. 5, pp. 740–750, 2004.

K. Kalita and T. Bezboruah, “Impact of gamma - optimization parameters and phase margin on closed loop gain of phase-locked loop,” International Journal of Electronics and Communication Engineering, vol. 6, no. 3, pp. 225–231, 2013.

N.A. Anang, Z. Jamaludin, L. Abdullah, M. Maharof and M.H. Nordin, “Robust Motion Controller Design for Precise Tracking of Ball Screw Driven Positioning System,” Journal of Advanced Manufacturing Technology, vol. 12, no. 1(4), pp. 73-85, 2018.

B. Daniels and R. Farrell, “Nonlinear Analysis of the 2nd Order Digital Phase Locked loop,” in IET Irish Signals and Systems Conference, NUI, Galway, 2008, pp. 66-71.

G.A. Leonov and N.V. Kuznetsov, Nonlinear Mathematical Models of Phase-Locked Loops, Stability and Oscillations (Stability Oscillations and Optimization of Systems). UK: Cambridge Scientific Publishers, 2014.

N. Margaris and P. Mastorocostas, “On the Nonlinear Behavior of the Analog Phase-Locked Loop:Synchronization,” IEEE Transaction on Industrial Electronics, vol. 43, no. 6, pp. 621–629, 1996.

B.C. Sarkar, S.S. De Sarkar and T. Banerjee, “Nonlinear dynamics of a class of symmetric lock range DPLLs with an additional derivative control,” Signal Processing, vol. 94, pp. 631–641, 2014.

A.J. Viterbi, Principles of coherent communications. New York: McGraw-Hill, 1966.

J. LaSalle and S. Lefschetz, Stability by Liapunov’s direct method with applications. New York: Academic Press, 1961.

D.Y. Abramovitch, “Lyapunov Redesign of Analog Phase-Lock Loops,” IEEE Transaction on Communications, vol. 38, no. 12, pp. 2197–2202, 1990.

N.E. Wu, “Circle/Popov Criteria in Phaselock Loop Design,” in Proceedings of the American Control Conference, Philadelphia, Pennsylvania, 1998, pp. 3226–3228.

D. Abramovitch, “Phase-Locked Loops: A Control Centric Tutorial,” in Proceedings of the American Control Conference, Anchorage, USA, 2002, pp. 1–15.

K. Zhou and J.C. Doyle, Essentials of robust control. New Jersey: Prentice Hall Upper, 1998.

A.I. Lur’e and V.N. Postnikov, “On the theory of stability of control systems,” Appllied Mathematics and Mechanics., vol. 8, no. 3, pp. 246–248, 1944.

J.C. Hsu, and A.U. Meyer, Modern control principles and applications. New York: McGraw-Hill, 1968.

A. Rantzer, “On the Kalman-Yakubovich-Popov lemma,” Systems and Control Letters, vol. 28, no. 1, pp. 7–10, 1996.

W. Tranter, T. Bose and R. Thamvichai, “Basic Simulation Models of Phase Tracking Devices Using MATLAB,” Synthesis Lectures on Communications, vol. 4, no. 1, pp. 1-136, 2010.

*Journal of Advanced Manufacturing Technology (JAMT)*,

*13*(2). Retrieved from https://jamt.utem.edu.my/jamt/article/view/5515